SRAM memory must have the following properties:
1- Addresses are from 0x8000 to 0x801F.
2- You can read and write one byte at a time.
3- The are special output signals that are required. They are listed in the table below.
Signal code Signal name Desciption
Z Zeros If all the bits in the sram are 0
O Ones If all the bits in the sram are 1
L Lower Ones
Upper Zeros
If 16 lower bytes of the sram are ones and the 16 upper parts of
the sram are zeros.
U Lower
Zeros Upper
Ones
If 16 lower bytes of the sram are zeros and the 16 upper parts of
the sram are ones.
Assume all nMOS and pMOS has (W= 4λ, L=2λ) unless it is nessesary to change sizing. The inputs
and outputs of your design are as follows:
Inputs: Outputs:
An unsigned 5-bit Address A (a4: a0) An unsigned 8-bit Data D (d7: d0)
An unsigned 8-bit Data D (d7: d0) Z,O,L,U.
Read, Write signals.
Phi1, Phi1_b, Phi2, Phi2_b for clocking.
Any other necessary outputs

 Part 3: Implement your design using Magic VLSI layout tool to generate your project layout
http://opencircuitdesign.com/magic/
 Part 4: Test your design using irsim to simulate your project.
http://opencircuitdesign.com/irsim/
Deliverables:
1- One PDF that contains the following sections:
 Introduction
 Problem statement and specifications
 Motivation
 Solution design using a logic design tool that you studied in the previous logic design courses
and HDL tool
Phase 2:
(by using logsim)
 Part 2: List in a table the required components with their respective input and output labels
structural method
 Part 1: Verify the design using a logic design tool and an HDL tool (using active HDL) using
Phase 1:
Requirement:
Any other necessary inputs
A common VDD and common GND lines
 Stick diagram for each component of your design. The building blocks components are
enough.
 Testing strategy and results: they should show instructions to simulate and verify your design,
by including Linux terminal