Scenario
Contiguous allocation of physical memory is eliminated by paging memory
management scheme. It allows the physical address space of a process to be
non–contiguous. A page table is used to track between page (logical address)
and frame (physical address). The hardware implementation of the page table
can be done by using dedicated registers. But the usage of the register for the
page table is satisfactory only if the page table is small. If the page table contains
a large number of entries then we can use TLB(translation Look-aside buffer), a
special, small, fast look-up hardware cache.
1-Analyse the address translation architecture aided with diagrams (how the physical address and logical address Mapping by page table)
2- relevant terminology And explain what is physical address, logical address ,register and how to implement
3- roles (what is the size of the register and what is the size of page)
4-What is the challenging issues,